The present invention is particularly intended for use in a system wherein data is conveyed in a multiplicity, such as eight, serial data streams on corresponding parallel lines so that the data lines constitute a synchronous parallel bus. For example, such a parallel bus may be employed for the transmission of data from one device or `chip` to another, a relatively wide parallel signal being converted group by group into corresponding serial groups which are transmitted on the respective lines of the synchronous parallel bus. In a particular example, the parallel digital signal may be sixty-four bits wide and each eight-bit group (i.e. byte) in the digital signal may be serialised and transmitted along a respective one of the lines of the parallel bus. At the receiver, or destination `chip`, the serial groups may be deserialised to reconstitute the data signal in its original wide parallel form.
Systems of this nature, and intended to deal with the problems of phase shift and byte alignment, are the subject of the above-mentioned earlier patent applications which are commonly assigned and are incorporated herein by reference.
High-speed serial links normally employ framing codes with redundancy, such as schemes known as 8B/10B, and also include cyclic redundancy codes for the detection of transmission errors. The main disadvantages of these schemes are the substantial transmission capacity (i.e. bandwidth) that they require. Furthermore, the complexities of implementing redundant encoders at very high operating frequencies are substantial.
The present invention is based on the use of an additional line, herein called a `control line`, in parallel with the high-speed parallel bus. Such a control line has a general utility, for example for the transmission of training patterns which may be employed, as suggested in the earlier applications, to maintain the data lines in synchronism. The object of the present invention is to provide framing codes on such a control line in a manner which employs a high degree of redundancy to provide error detection and preferably includes a parity check, so that coding redundancy or cyclic redundancy code protection in the data signal is not required, the corresponding bandwidth being saved.